1. Field of the Invention
The present invention relates to an electronic circuit that is capable of suitably carrying out communications between substrates such as IC (Integrated Circuit) bare chips, and PCB (Printed Circuit Boards).
2. Description of the Related Art
The inventor et al. have proposed to achieve a system-in-package (SiP) for sealing a plurality of bare chips in one package of LSI (Large-Scale Integration) by a method for three-dimensionally mounting chips and electrically connecting chips to each other by inductive coupling (see Patent Document 1).
FIG. 5 is a view depicting a configuration of an electronic circuit according to the invention in Japanese earlier application. The electronic circuit is composed of the first through the third LSI chips 31a through 31c. This is an example in which LSI chips are stacked up in three layers and a bus is formed so as to lie across three chips. That is, a single communication channel capable of carrying out communications among the three (three LSI chips) is constructed. The first LSI chip 31a through the third LSI chip 31c are vertically stacked up, and the respective chips are fixed to each other with an adhesive agent. The first transmitter coil 33a through the third transmitter coil 33c, which are respectively used for transmission, are formed by wiring on the first LSI chip 31a through the third LSI chip 31c, and also, the first receiver coil 35a through the third receiver coil 35c, which are respectively used for receiving, are formed by wiring thereon. The three pairs of transmitter and receiver coils 33 and 35 are disposed on the first LSI chip 31a through the third LSI chip 31c so that the centers of openings of the transmitter and receiver coils 33 and 35 are made coincident with each other. Accordingly, the three pairs of transmitter and receiver coils 33 and 35 form inductive coupling, thereby enabling communications. The first transmitter circuit 32a through the third transmitter circuit 32c are connected to the first transmitter coil 33a through the third transmitter coil 33c respectively, and the first receiver circuit 34a through the third receiver circuit 34c are connected to the first receiver coil 35a through the third receiver coil 35c respectively. The transmitter and receiver coils 33 and 35 are three-dimensionally mounted as coils having one or more windings in an area permitted for communications, utilizing a multi-layered wiring of a process technology. A profile best suitable for communications exists in the transmitter and receiver coils 33 and 35, and it is necessary that they have an optimal number of times of winding, optimal opening, and optimal line width. Generally, the transmitter coils 33 are smaller than the receiver coils 35.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-228981